See larger image

Introduction to Semiconductor Manufacturing Technology

Hong Xiao, Ph. D.

Published by Prentice Hall

Reviewers comments 

1.     Introduction (PowerPoint Preview)

2.    Introduction of IC Fabrication

3.    Semiconductor Basics  (PowerPoint Preview)

4.      Wafer Manufacturing

5.      Thermal Processes

6.      Photolithography

7.      Plasma Basics

8.      Ion Implantation

9.      Etch

10.  CVD and Dielectric Thin Film

11.  Metallization

12.  CMP

13.  Process Integration

14.  CMOS Processes

15. Future Trends and Summary (PowerPoint Preview)

Index

1.      Introduction

1.1.            Brief History

1.1.1.      First Transistor

1.1.2.      First Integrated Circuit

1.1.3.      Moore’s Law

1.1.4.      Feature Size and Wafer Size

1.2.            Brief Overview

1.2.1.      Manufacture Materials

1.2.2.      Process Equipment

1.2.3.      Metrology Tools

1.2.4.      Wafer Manufacturing

1.2.5.      Circuit Design

1.2.6.      Mask Making

1.2.7.      Wafer Processing

1.2.8.      Testing

1.2.9.      Packaging and Test

Review Questions

Reference

2.      Introduction of IC Fabrication

2.1.            Introduction

2.2.            Yield

2.2.1.      Definition of Yield

2.2.2.      Yield and Profit Margin

2.2.3.      Defects and Yield

2.3.            Cleanroom Basic

2.3.1.      Definition of cleanroom

2.3.2.      Contamination Control and Yield

2.3.3.      Basic Cleanroom Structure

2.3.4.      Basic Cleanroom Gowning Procedural

2.3.5.      Basic Cleanroom Protocol

2.4.            Basic Structure of IC Fab

2.4.1.      Wafer Process Area

Wet bay

Diffusion bay

Photo bay

Etch bay

Implant bay

Thin film bay

CMP bay

2.4.2.      Equipment Area

2.4.3.      Facility Area

2.5.            Test and Packaging

2.5.1.      Die Test

2.5.2.      Chip Packaging

2.5.3.      Final Test

2.6.            Fab Trends

2.7.            Summary

Review Questions

References

3.      Semiconductor Basics

3.1.            What is a Semiconductor

3.1.1.      Band Gap

3.1.2.      Crystal Structure

3.1.3.      Doping Semiconductor

3.1.4.      Dopant Concentration and Conductivity

3.1.5.      Summary of Semiconductor

3.2.            Basis Devices

3.2.1.      Resistor

3.2.2.      Capacitor

3.2.3.      Diode

3.2.4.      Bipolar Transistors

3.2.5.      MOSFETs

3.2.6.       

3.3.            IC Chips

3.3.1.      Memory

DRAM

SRAM

EPROM, EEPROM

3.3.2.      Microprocessor

3.3.3.      ASIC

3.4.            Basis IC Processes

3.4.1.      Conventional Bipolar Process

3.4.2.      PMOS Process (1960s Technology)

3.4.3.      NMOS Process (1970s Technology)

3.5.            CMOS

3.5.1.      CMOS circuit

3.5.2.      CMOS Process (1980s Technology)

3.6.            Technology Trends After 1990s

3.7.            Summary

Review Questions

References

4.      Wafer Manufacturing

4.1.            Introduction

4.2.            Why silicon

4.3.            Crystal structure and Defects

4.4.            From sand to Wafer

4.5.            Epitaxial deposition

4.6.            Summary

Review Questions

References

5.      Thermal Processes

5.1.            Introduction

5.2.            Thermal Process Hardware

5.3.            Oxidation

5.3.1.      Introduction

5.3.2.      Applications

5.3.3.      Pre-oxidation Clean

5.3.4.      Oxidation Rate

5.3.5.      Dry oxidation

5.3.6.      Wet oxidation

5.3.7.      High pressure oxidation

5.3.8.      Oxide Measurement

5.3.9.      Oxidation Trends

5.4.            Diffusion

5.4.1.      Diffusion Basic

5.4.2.      Deposition and Drive-in

5.4.3.      Doping Measurement

5.5.            Annealing

5.5.1.      Post Implantation Annealing

5.5.2.      Alloy annealing

5.5.3.      Reflow

5.6.            High temperature CVD

5.6.1.      Epitaxial Silicon Deposition

5.6.2.      Polycrystalline Silicon Deposition

5.6.3.      Silicon Nitride Deposition

5.7.            Rapid thermal process (RTP)

5.7.1.      RTP System

5.7.2.      Rapid Thermal Anneal (RTA)

5.7.3.      Rapid Thermal Oxidation (RTO)

5.8.            Future Trends

5.9.            Summary

Review Questions

Reference

6.      Photolithography

6.1.            Introduction

6.2.            Photoresist

6.3.            Photolithography process

6.3.1.      Wafer clean

6.3.2.      Preparation

6.3.3.      Photoresist Coating

6.3.4.      Soft bake

6.3.5.      Alignment and exposure

Contact and Proximity Printers

Projection Printer

Stepper

Exposure Light Sources

Exposure Control

6.3.6.      Post Exposure Bake

6.3.7.      Development

6.3.8.      Hard Bake

6.3.9.      Pattern Inspection

6.4.            Lithography Technology Trends

6.4.1.      Resolution and depth of focus (DOF)

6.4.2.      I-line, DUV and EUV

6.4.3.      Phase-Shift Mask

6.4.4.      EUV Lithography

6.4.5.      X-ray Lithography

6.4.6.      Electron Beam Lithography

6.4.7.      Ion Beam Lithography

6.5.            Safety

6.6.            Summary

Review Questions

References

7.      Plasma Basics

7.1.            Introduction

7.2.            Definition of Plasma

7.2.1.      Definition

7.2.2.      Components of Plasma

7.2.3.      Generation of Plasma

7.3.            Collisions in Plasma

7.3.1.      Ionization Collision

7.3.2.      Excitation-Relaxation

7.3.3.      Other Collisions

7.4.            Plasma Parameters

7.4.1.      Mean-free-path (MFP)

7.4.2.      Thermal Velocity

7.4.3.      Magnetic Field

7.4.4.      Boltzmann Distribution

7.5.            Ion bombardment

7.6.            DC-bias

7.7.            Advantages of Plasma Processes

7.7.1.      CVD

7.7.2.      Plasma Etch

7.7.3.      Sputtering Deposition

7.8.            PECVD and Plasma Etch Chambers

7.8.1.      The Differences

7.8.2.      Chamber Design

7.9.            Remote Plasma Processes

7.9.1.      Photoresist strip

7.9.2.      Remote Plasma Etch

7.9.3.      Remote Plasma Clean

7.9.4.      Remote Plasma CVD

7.10.        High Density Plasma

7.10.1.  Inductive Coupled Plasma (ICP)

7.10.2.  Electron Cyclotron Resonance (ECR)

7.11.        Summary

Review Questions

References

8.      Ion Implantation

8.1.            Introduction,

8.1.1.      Brief History

8.1.2.      Advantage of Implantation

8.1.3.      Applications

8.2.            Ion Implantation Basics

8.2.1.      Stopping Mechanisms

8.2.2.      Ion Range

8.2.3.      Channeling Effect

8.2.4.      Damaging and Annealing

8.3.            Ion Implantation Hardware

8.3.1.      Gas System

8.3.2.      Electrical System

8.3.3.      Vacuum System

8.3.4.      Control System

8.3.5.      Beam Line System

Ion Source

Extraction

Analyzer

Post Acceleration

Charge Neutralization Systems

Wafer Handlers

Beam Stop

8.4.            Ion Implantation Processes

8.4.1.      Device Applications

8.4.2.      Process Issues

Wafer Charging

Particle Contamination

Elemental Contamination

8.4.3.      Process Evaluation

8.4.3.1.            Thermal Wave

8.4.3.2.            Optical Measurement System

8.5.            Safety

8.5.1.      Chemical Hazards

8.5.2.      Electrical Hazards

8.5.3.      Radiation Hazards

8.5.4.      Mechanical Hazards

8.6.            Technology Trends

8.7.            Summary

Review Questions

References

9.      Etch

9.1.            Introduction

9.2.            Etch Basic

9.2.1.      Etch Rate

9.2.2.      Uniformity

9.2.3.      Selectivity

9.2.4.      Profile

9.2.5.      Loading effects

Macro Loading

Micro Loading

9.2.6.      Over Etch

9.2.7.      Residue

9.3.            Wet Etch Process

9.3.1.      Introduction

9.3.2.      Oxide Wet Etch

9.3.3.      Silicon Etch

9.3.4.      Nitride Etch

9.3.5.      Metal Etch

9.4.            Plasma (Dry) Etch

9.4.1.      Plasma Review

9.4.2.      Chemical, Physical and Reactive Ion Etches

9.4.3.      Etch Mechanisms

9.4.4.      Plasma Etch Chambers

9.4.5.      Endpoint

9.5.            Plasma Etch Processes

9.5.1.      Dielectric Etch

9.5.2.      Single Crystal Silicon Etch

9.5.3.      Polysilicon Etch

9.5.4.      Metal etch

9.5.5.      Photoresist Strip

9.5.6.      Dry Chemical Etch Processes

9.5.7.      Blanket etch processes

9.5.8.      Safety

9.6.            Future Trends

9.7.            Summary

Review questions

References

10.  CVD and Dielectric Thin Film

10.1.        Introductions

10.2.        Chemical Vapor Deposition (CVD)

10.2.1.  CVD Process Description

10.2.2.  CVD Reactor Types

APCVD

LPCVD

PECVD

10.2.3.  CVD basics

Step Coverage

Gap Fill

10.2.4.  Surface Adsorption

Chemisorption

Physisorption

10.2.5.  CVD Kinetics

Chemical Reaction Rate

Surface-Reaction-Limited Regime

Mass-Transport-Limited Regime

CVD Reactor Deposition Regime

10.3.        Applications of Dielectric Thin Film

10.3.1.  STI

10.3.2.  Sidewall Spacer

10.3.3.  PMD

10.3.4.  IMD

10.3.5.  Passivation Dielectric

10.4.        Dielectric Thin Film Characteristics

10.4.1.  Refractive Index

Ellipsometry

Prism Coupler

10.4.2.  Thickness

Color Chart

Spectroreflectometry

Deposition Rate

Wet Etch Rate

Shrinkage

Uniformity

10.4.3.  Stress

10.5.        Dielectric CVD Processes

10.5.1.  Thermal Silane CVD Process

10.5.2.  Thermal TEOS CVD Process

10.5.3.  PECVD Silane Processes

Passivation

PMD Barrier Layer

Dielectric Anti-Reflective Coating

10.5.4.  PECVD TEOS Processes

10.5.5.  Dielectric Etchback Processes

10.5.6.  O₃-TEOS Processes

Ozonator

O₃-TEOS USG Process

O₃-TEOS PSG and BPSG Processes

10.6.        Spin-on Glass

10.7.        High Density Plasma CVD

10.8.        Dielectric CVD Chamber Clean

10.8.1.  RF Plasma Clean

10.8.2.  Remote Plasma Clean

10.9.        Process Trends and Troubleshooting

10.9.1.  Silane PECVD Process Trends

10.9.2.  PE-TEOS Trends

10.9.3.  O₃-TEOS Trends

10.10.    Future Trends

10.10.1.                      Low-k Dielectrics

10.10.2.                      High-k Dielectrics

10.11.    Summary

Review Questions

References

11.  Metallization

11.1.        Objectives

11.2.        Introduction

11.3.        Conducting Thin Films

11.3.1.  Polysilicon

11.3.2.  Silicides

11.3.3.  Aluminum

11.3.4.  Titanium

11.3.5.  Titanium Nitride

11.3.6.  Tungsten

11.3.7.  Copper

11.3.8.  Tantalum

11.4.        Metal Thin Film Characteristics

11.4.1.  Deposition Rate

11.4.2.  Uniformity

11.4.3.  Stress

11.4.4.  Reflectivity

11.4.5.  Sheet resistance

11.5.        Metal CVD

11.5.1.  Introduction

11.5.2.  Tungsten

11.5.3.  Tungsten Silicide

11.5.4.  Titanium

11.5.5.  Titanium Nitride

11.5.6.  Aluminum

11.6.        Physical Vapor Deposition (PVD)

11.6.1.  Introductions

11.6.2.  Evaporation Processes

Thermal evaporation

Electron beam evaporation

11.6.3.  Sputtering

11.6.4.  Basic Metallization Processes

Degas

Pre-clean

Titanium PVD

Titanium Nitride PVD

Al-Cu PVD

11.7.        Copper Metallization

11.7.1.  Introduction

11.7.2.  Barrier Layer PVD

11.7.3.  Copper Seed Layer PVD

11.7.4.  Electrochemical Plating (ECP)

11.7.5.  Copper CVD

11.8.        Safety

11.9.        Summary

Review Questions

References

12.  CMP

12.1.        Objectives

12.2.        Introduction

12.2.1.  Definition of Planarization

12.2.2.  Other Planarization Methods

12.3.        CMP Hardware

12.3.1.  Introduction

12.3.2.  Polishing Pad

12.3.3.  Polishing Head

12.3.4.  Pad Conditioner

12.4.        CMP Slurries

12.4.1.  Oxide Slurry

12.4.2.  Tungsten Slurry

12.4.3.  Aluminum and Copper Slurries

12.5.        CMP Basics

12.5.1.  Polish Rate

12.5.2.  Selectivity

12.5.3.  Uniformity

12.5.4.  Defects

12.6.        CMP Processes

12.6.1.  Oxide CMP

12.6.2.  Tungsten CMP

12.6.3.  Copper CMP

12.6.4.  CMP Endpoint Detection

12.6.5.  Post-CMP Clean

12.7.        Safety

12.8.        Summary

Review Questions

References

13.  Process Integration

13.1.        Objectives

13.2.        Introduction

13.3.        Wafer Preparation

13.4.        Well Formation

13.4.1.  Single Well

13.4.2.  Self-aligned Twin Well

13.4.3.  Twin Well

13.5.        Isolations

13.5.1.  Blanket Field Oxide

13.5.2.  LOCOS

13.5.3.  STI

13.6.        Transistors Making

13.6.1.  None Self-aligned Gate Process

13.6.2.  Self-aligned Gate Process

13.6.3.  Lightly Doped Drain (LDD)

13.6.4.  Threshold Adjust

13.6.5.  Anti Punch-through

13.6.6.  Metal and High-k Gate MOS

13.7.        Interconnections

13.7.1.  Local Interconnection

13.7.2.  Early Interconnection

13.7.3.  Traditional Multi-level Interconnection

13.7.4.  Copper Interconnection

13.7.5.  Copper and Low-k

13.8.        Passivation

13.9.        Summary

Review Questions

References

14.  CMOS Processes

14.1.        Objectives

14.2.        IC Process Flow of the 1980s

14.2.1.  Isolation

14.2.2.  Well Formation

14.2.3.  Making Transistors

14.2.4.  Interconnections

14.3.        Advanced CMOS Process Flow (1990s Technology)

14.3.1.  Comments

14.4.        State-of-art CMOS Process Flow (2000's Technology)

14.5.        Summary

Review Questions

References

15.  Future Trends and Summary

Index