| This page is for informational purposes only. An official syllabus is provided the first day of class. |
| Course Description |
An introductory course in the layout and design of integrated circuits. This is the first of three courses designed to train students to become IC Layout Designers; however, this course may also be taken as a technical elective for other degree plans. An overview of the IC design and manufacturing process is provided with an emphasis on CMOS technology. Students learn to interpret logic gate symbols as well as the schematics of basic circuits. Instruction includes helping students to construct layouts beginning with the simple and progressing to the complex. Students receive training in Cadence Virtuoso to compose their layouts. To insure proper layout construction both physically and electrically, DRC and LVS verification is introduced. |
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| Rationale |
This course is intended to give students workforce skills in the CAD field.
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| Instructional Methodology |
- Lectures introduce new material.
- Exercises allow the instructor to lead students through the material the first time.
- Projects provide opportunities for students to practice with the new tools on their own.
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| Prerequisites |
DFTG 2419, DFTG 1458, or Instructor approval. May be taken concurrently with CETT 1409. CETT 1425 recommended. |
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| Objectives/Outcomes |
To teach the students to interpret design schematics and convert the schematics to CMOS design masks using the Cadence Virtuoso Layout editing tool. The students will learn how to minimize the design size, minimize the negative effects of unavoidable parasitic elements and effectively use the design tool to minimize the time to complete a design. |
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| Grade Determination |
Grading policies are determined by individual instructors or course coordinators. |
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