| This page is for informational purposes only. An official syllabus is provided the first day of class. |
| Course Description |
An advanced course in the layout and design of integrated circuits. Students will study advanced design theory and employ specialized CAD tools to layout and verify circuits. |
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| Rationale |
This course is intended to give students workforce skills in the CAD field.
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| Instructional Methodology |
- Lectures introduce new material.
- Exercises allow the instructor to lead students through the material the first time.
- Projects provide opportunities for students to practice with the new tools on their own.
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| Prerequisites |
DFTG 2470. May be taken concurrently with CETT 1425. |
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| Objectives/Outcomes |
To teach the students 1)to interpret design schematics and convert the schematics to CMOS design masks using the Cadence Virtuoso Layout editing tool. 2)to run DRC/LVS verifying their layout designs using Cadence Diva and Dracula. 3)to learn how to minimize the design size, minimize the negative effects of unavoidable parasitic elements, latch up and electromigration. 4)to effectively use the design tool to minimize the time to complete a design. |
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| Grade Determination |
Grading policies are determined by individual instructors or course coordinators. |
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View A&E CAD departmental Policies and Procedures
View SCANS Competencies for all A&E CAD courses
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